J. De Vos, C. Hocquet, F.Botman, F. Durvaux, S. Boyd, D. Flandre
and J.-D. Legat, “A 25MHz 7µW/MHz Ultra-Low-Voltage
Microcontroller SoC in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor
Nodes”, in Proc. IEEE Int. Solid-State Circuits Conf., pp. 490-491, 2012]
|Sleepwalker SoC (UCL1210_SW)
is a 65nm microcontroller SoC for low-carbon wireless sensor nodes
(WSNs). The design target was to minimize the carbon footprint of
the SoC over the whole life cycle through minimization of:
while ensuring robust operation at 25MHz.
- embodied energy for chip manufacturing,
- energy per operation in active mode,
- power in stand-by mode,
ultra-low-voltage design at 0.4V (near-Vt) in 65nm LP/GP CMOS with
special techniques for robustness, energy efficiency and low die area.
Embodied energy is estimated at 195kJ/die (0.66mm²) while measurements
results show a electrical energy consumption in active mode as low as
and a power in stand-by mode of 1.5µW. Robust 25MHz operation over PVT
corners is ensured by an all-digital on-chip adaptive voltage scaling
(AVS) system. The SoC only requires a single supply voltage (1-1.2V)
single crystal clock (32-100kHz).
[C. Hocquet, D. Kamel, F. Regazzoni, J.-D. Legat, D. Flandre, D.
Bol and F.-X. Standaert, “Harvesting the potential of nano-CMOS for
lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for
passive RFID tags”, in Springer J. Cryptographic Engineering, vol. 1, no. 1, pp. 79-89, 2011]
|AES coprocessor (UCL1109_AES8)|
this 65nm test chip is implemented an ultra-low-votlage (ULV) AES
coprocessor for smart RFID applications. The design target was to
demonstrate important energy savings without complex algorithm nor
architecture design. Measurement results show correct functionality for
20 dies down to 0.32V with an energy per encryption as low as 8.5pJ/bit
Several versions of the AES coprocessor were implemented on this test
chip to test the efficiency of design techniques aiming at ensuring
functionality at ULV. Gate length upsize and single-stage buffered
clock tree were implemented to mitigate degraded logic levels and
hold-time violations induced by clock skew variability.
[D. Bol, “Robust and energy-efficient
ultra-low-voltage circuit design under timing constraints in 65/45nm CMOS”
(invited), in MDPI J. Low-Power
Electronics and Applications,
vol. 1, no .1, pp. 1-19, 2011]