[G. de Streel, F. Stas, T. Gurné, F. Durant, C. Frenkel and D. Bol, “SleepTalker: a 28nm FDSOI ULV 802.15.4a IR-UWB Transmitter SoC achieving 14pJ/bit at 27Mb/s with Adaptive-FBB-based Channel Selection and Programmable Pulse Shape”, in Proc. IEEE Symp. VLSI Circuits, 2 p., 2016]
SleepTalker SoC

 SleepTalker is a 28nm FDSOI 0.55V impulse-radio UWB transmitter SoC for high-data-rate/low-latency wireless sensor nodes (WSNs). It achieves a record energy efficiency of 14pJ/bit with embedded power management including DC/DC converter and charge-pump boost generators, highly duty cycled digital baseband processor, digitally-programmable pulse shaping and wide-range on-chip adaptive forward back biasing (FBB) for Vt reduction, PVT compensation and tuning of both the carrier frequency (CF) and the output power.









 

[D. Bol, G. de Streel, F. Botman, A. Kuti Lusala and N. Couniot, “A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range”, in Proc. IEEE Symp. VLSI Circuits, pp. 180-182, 2014]
 [F. Botman, J. de Vos, S. Bernard, F. Stas, J.-D. Legat and D. Bol, “Bellevue: a 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes”, in Proc. IEEE Int Conf. Circuits and Systems, pp. 1207-1210, 2014]
[D. Bol, E.H. Boufouss, D. Flandre and J. De Vos, “A 0.48mm˛ 5μW-10mW Indoor/Outdoor PV Energy-Harvesting Management Unit in a 65nm SoC based on a Single Bidirectional Multi-Gain/Multi-Mode Switched-Cap Converter with Supercap Storage”, in Proc. European Solid-State Circ. Conf., pp. 241-244, 2015]
 SunPixer SoC

SunPixer is a 65nm solar-powered video monitoring SoC for Internet-of-Things visual sensor nodes. It embeds:
  • 0.5V digital-pixel-sensor (DPS) CMOS imager with 42dB dynamic range thanks to time-base readout supplied,
  • an ultra-low-quiescient-current linear voltage regulator with a ΔVT 0.2V to 1V  9.7nW voltage reference, 
  • a 50-MHz 0.37V 32-bit SIMD microcontroller with 64kB SRAM including on-chip DC/DC conversion and second-generation adaptive voltage scaling  (AVS) system,
  • 5μW-10mW energy-havesting PMU based on direct harvester-load connection and a birectionnal multi-gain/multi-mode switched- capacitor  for indoor/outdoor micro PV harvesters and supercapacitor energy storage.
[G. de Streel, J. De Vos and D. Bol, “A ΔVT 0.2V to 1V 0.01mm˛ 9.7nW Voltage Reference in 65nm LP/GP CMOS”, in Proc. IEEE SOI-3D-Subthreshold Microelectronics Tech. Unified Conf., 2 p., 2015]
[G. de Streel, J. De Vos, D. Flandre and D. Bol, “A 65nm 1V to 0.5V linear regulator with ultra-low quiescent current for mixed-signal ULV SoCs”, in Proc.  IEEE FTFC Conference, 4 p., 2014]

[D. Bol, J. De Vos, C. Hocquet, F.Botman,  F. Durvaux, S. Boyd, D. Flandre and J.-D. Legat, “A 25MHz 7µW/MHz Ultra-Low-Voltage Microcontroller SoC in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes”, in Proc. IEEE Int. Solid-State Circuits Conf., pp. 490-491, 2012]
 SleepWalker SoC
SleepWalker is a 65nm 16-bit microcontroller SoC for low-carbon wireless sensor nodes (WSNs). The design target was to minimize the carbon footprint of the SoC over the whole life cycle through minimization of:
  •     embodied energy for chip manufacturing,
  •     energy per operation in active mode,
  •     power in stand-by mode,
while ensuring robust operation at 25MHz.

This is achieved through ultra-low-voltage design at 0.4V (near-Vt) in 65nm LP/GP CMOS with special techniques for robustness, energy efficiency and low die area. Embodied energy is estimated at 195kJ/die (0.66mm˛) while measurements results show a electrical energy consumption in active mode as low as 7pJ/cycle and a power in stand-by mode of 1.5µW. Robust 25MHz operation over PVT corners is ensured by an all-digital on-chip adaptive voltage scaling (AVS) system. The SoC only requires a single supply voltage (1-1.2V) and a single crystal clock (32-100kHz).
[C. Hocquet, D. Kamel, F. Regazzoni, J.-D. Legat, D. Flandre, D. Bol and F.-X. Standaert, “Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags”, in Springer J. Cryptographic Engineering, vol. 1, no. 1, pp. 79-89, 2011]
 AES coprocessor
On this 65nm test chip is implemented an ultra-low-votlage (ULV) AES coprocessor for smart RFID applications. The design target was to demonstrate important energy savings without complex algorithm nor architecture design. Measurement results show correct functionality for 20 dies down to 0.32V with an energy per encryption as low as 8.5pJ/bit @100kbps/0.4V.

Several versions of the AES coprocessor were implemented on this test chip to test the efficiency of design techniques aiming at ensuring functionality at ULV. Gate length upsize and single-stage buffered clock tree were  implemented to mitigate degraded logic levels and hold-time violations induced by clock skew variability.

[D. Bol, “Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45nm CMOS” (invited), in MDPI J. Low-Power Electronics  and Applications, vol. 1, no .1, pp. 1-19, 2011]