this page, we provide pre-silicon compact MOSFET models for early SPICE
simulations. They allows designers from fabless companies and academia
to perform SPICE simulations before the technology gets mature, in
order to be ready to face new design challenges when circuit
prototyping will be available.
| MOSFET models of 45nm CMOS processes for subthreshold operation
These models are BSIM4 model cards based on PTM (NanoCMOS tool) models
and are refined to realistically represent subthreshold operation. They
include the three process flavors aligned on ITRS targets are available
in bulk technology (HP, LOP and LSTP) and one process flavor (HP) in
fully-depleted SOI technology.
Models: UCL-SubVt45 (released May 2010).
- D. Bol, D. Flandre and J.-D. Legat, “Nanometer
MOSFET effects on the minimum-energy point of sub-45nm subthreshold logic—Mitigation
at technology and circuit levels”, in ACM
Trans. Design Automation of Electronic Syst., vol. 16, no. 1, pp. 2-26,
- D. Bol, D. Kamel, D.
Flandre and J.-D. Legat: “Nanometer MOSFET effects on the
minimum-energy point of 45nm subthreshold logic”, in Proc.
IEEE/ACM International Symposium Low-Power Electronics and Design, pp.
3-8, 2009. [pdf]
- D. Bol, R. Ambroise,
D. Flandre and J.-D. Legat: “Sub-45nm fully-depleted SOI CMOS
subthreshold logic for ultra-low-power applications”, in Proc.
IEEE International SOI Conference, 2 p., 2008. Best poster award. [pdf]
MOSFET models of 22/20nm CMOS processes for bulk vs. fully-depleted SOI comparison
These models are BSIM4 and BSIM4SOI model cards based on PTM22LP v2.1.
They are generated to fairly compare bulk and fully-depeted SOI at
22/20nm node for low-power digital applications (logic and SRAM).
Current model version includes LSTP process flavor aligned on ITRS 2010
Models: UCL-LSTP22_V4.4 (released September 2011).
Bol, S. Bernard and D. Flandre, “Pre-silicon 22/20nm compact MOSFET
models for bulk vs. FD SOI low-power circuit benchmarks”, in Proc.
IEEE International SOI Conference, 2 p., 2011.