Papers in scientific journals

• D. Bol, J. De Vos, C. Hocquet, F. Botman, F. Durvaux, S. Boyd, D. Flandre and J.-D. Legat, “SleepWalker: a 25-MHz 0.4-V sub-mm² 7-µW/MHz microcontroller in 65-nm LP/GP CMOS for low-carbon wireless sensor nodes”, in IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 20-32, 2013. [pdf]
• D. Bol, C. Hocquet and F. Regazzoni, “A fast ULV logic synthesis flow in many-Vt CMOS processes for minimum energy under timing constraints”, in IEEE Trans. Circuits and Syst. II, vol. 59, no. 12, pp. 947-951, 2012. [pdf]
• D. Kamel, M. Renauld, D. Bol, F.-X. Standaert and D. Flandre, “Analysis of dynamic differential swing limited logic for low-power secure applications”, in MDPI J. Low-Power Electronics and Applications, vol. 2, no. 1, pp. 98-126, 2012. [pdf]
• J. De Vos, D. Flandre and D. Bol, “Pushing Adaptive Voltage Scaling Fully On Chip”, in AP J. Low-Power Electronics, vol. 8, no. 1, pp. 95-112, 2012.
  
• D. Bol, “Robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 65/45nm CMOS” (invited), in MDPI J. Low-Power Electronics  and Applications, vol. 1, no .1, pp. 1-19, 2011. [pdf]
• C. Hocquet, D. Kamel, F. Regazzoni, J.-D. Legat, D. Flandre, D. Bol and F.-X. Standaert, “Harvesting the potential of nano-CMOS for lightweight cryptography: An ultra-low-voltage 65 nm AES coprocessor for passive RFID tags”, in Springer J. Cryptographic Engineering, vol. 1, no. 1, pp. 79-89, 2011. [pdf]
• D. Bol, D. Flandre and J.-D. Legat, “Nanometer MOSFET effects on the minimum-energy point of sub-45nm subthreshold logic—Mitigation at technology and circuit levels”, in ACM Trans. Design Automation of Electronic Syst., vol. 16, no. 1, pp. 2-26, 2010. [pdf]
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Interests and limitations of technology scaling for subthreshold logic”, in IEEE Trans. VLSI Systems, vol. 17, no. 10, pp. 1508-1519, 2009. [pdf] Compact models are available here.
• D. Bol, J. De Vos, R. Ambroise, D. Flandre and J.-D. Legat: “Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology”, in Solid-State Electronics, vol. 52, no. 8, pp. 1939-1945, 2008. [pdf]
• D. Bol, I. Hassoune, D. Levacq, D. Flandre and J.-D. Legat: “Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS structures”, in Journal of Multiple-Valued Logic and Soft Computing, vol. 13, pp. 61-76, 2007. 
• Ph. Manet, R. Ambroise, D. Bol, M. Baltus and J.-D. Legat: “Low power techniques applied to a 80C51 microcontroller for high temperature applications”, in Journal of Low Power Electronics, vol. 2 (1), pp. 95-104, 2006. 
• I. Hassoune, A. Drummond, A. Gaudissart, D. Bol, D. Levacq, D. Flandre and J.-D. Legat: “A new multi-valued current-mode adder based on negative-differential resistance using ULP diodes”, in Solid-State Electronics, vol. 49, pp. 1185-1191, 2005.  [pdf]

Book chapter

• D. Bol, “Ultra-Low-Voltage Design of Nanometer CMOS Circuits  for Smart Energy-Autonomous Systems”, in Advanced Circuits for Emerging Technologies, K. Iniewski (Ed.), Wiley, pp. 57-83, 2012. [pdf]

Contributions in international conferences

• J. De Vos, D. Bol and D. Flandre, “A dual-mode DC/DC converter for ultra-low-voltage microcontrollers”, in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2012.
  
• F. Botman, D. Bol, C. Hocquet and J.-D. Legat “Data-dependent operation speed-up through automatically-inserted signal transition detectors for ultra-low voltage logic circuits”, in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2012.
• D. Bol, V. Kilchytska, J. De Vos, F. Andrieu and D. Flandre, “Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications”, in Proc. IEEE International SOI Conference, 2p. , 2012.
  
• S. Kerckhof, F. Durvaux, C. Hocquet, D. Bol and F.-X. Standaert, “Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint, in Proc. Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, vol. 7428, pp 390-407, 2012.
  
• G. de Streel, D. Bol and J.-D. Legat, “Multi-VT ultra-low-power FPGA implementation in 65nm CMOS technology, in Proc. Workshop Faible Tension Faible Consommation (FTFC), 4 p., 2012. [pdf]
• D. Bol, J. De Vos, C. Hocquet, F.Botman,  F. Durvaux, S. Boyd, D. Flandre and J.-D. Legat, “A 25MHz 7µW/MHz Ultra-Low-Voltage Microcontroller SoC in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes”, in Proc. IEEE Int. Solid-State Circuits Conf., pp. 490-491, 2012. [pdf]
• D. Bol, S. Bernard and D. Flandre, “Pre-silicon 22/20nm compact MOSFET models for bulk vs. FD SOI low-power circuit benchmarks”, in Proc. IEEE International SOI Conference, 2p., 2011. [pdf]
• J. De Vos, D. Bol and D. Flandre, "Design methodology for sizing DCDC converters supplying subthreshold circuits", in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2011. [pdf]
• C. Hocquet, F. Botman, J.-D. Legat and D. Bol, "A near-threshold instruction cache with zero miss overhead time for dual-Vdd microcontrollers", in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2011. 
• D. Bol, C. Hocquet, J. De Vos, F. Durvaux, F. Botman, D. Flandre and J.-D. Legat , "Design techniques for reliable timing closure in ULV SoCs", in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2011.
• F. Botman, D. Bol, C. Hocquet and J.-D. Legat "Exploring the Opportunity of Operating a COTS FPGA at 0.5V", in Proc. IEEE Subthreshold Microelectronics Conference, 2 p., 2011. [pdf]
• A. Barenghi, C. Hocquet, D. Bol, F.-X. Standaert, F. Regazzoni and I. Koren, “Exploring the feasibility of low cost fault injection attacks on sub-threshold devices through an example of a 65nm AES implementation”, in Proc. RFIDSec Workshop on RFID Security and Privacy, 14 p., 2011.
• J. De Vos, D. Flandre and D. Bol, “Variability and ripple analysis of an on-chip all-digital AVS system”, in Proc. VARI Workshop on CMOS Variability, 4 p., 2011. [pdf]
• D. Bol, S. Boyd and D. Dornfeld: “Application-aware LCA of semiconductors: life-cycle energy of microprocessors from high-performance 32nm CPU to ultra-low-power MCU”, in Proc. IEEE International Symposium on SUstainable Systems and Technologies, 6 p., 2011. [pdf]
• G. Gosset, D. Bol, G. Pollissard-Quatremère, B. Rue and D. Flandre: “Disruptive ultra-low-power SOI CMOS circuits towards µW medical sensor implants”, in Proc. IEEE International SOI Conference, 2 p., 2010. [pdf]
  
• D. Bol, C. Hocquet, D. Flandre and J.-D. Legat: “The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic”, European Solid-State Circuits Conference, pp. 522-525, 2010. [pdf]
• D. Kamel, C. Hocquet, F.-X. Standaert, D. Flandre and D. Bol: “Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits”, European Solid-State Circuits Conference, pp. 518-521, 2010.  [pdf]
• J. De Vos, D. Bol and D. Flandre: “Dual-mode switched-converter DC-DC converter for subthreshold processor with deep sleep mode”, Fringe poster session at the European Solid-State Circuits Conference, 4p., 2010.  [pdf]
• D. Bol, C. Hocquet, D. Flandre and J.-D. Legat: “Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits”, Proc. IEEE International Symposium on Circuits and Systems, pp. 1484-1487, 2010. [pdf]
• D. Bol, J. De Vos, D. Flandre and J.-D. Legat: “Ultra-low-power high-noise-margin logic with undoped FD SOI devices”, in Proc. IEEE International SOI Conference, pp. 97-98, 2009. [pdf]
• D. Bol, D. Flandre and J.-D. Legat: “Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits”, in Proc. IEEE/ACM International Symposium Low-Power Electronics and Design, pp. 21-26, 2009. Acceptance rate: 24%.  [pdf]
• D. Bol, D. Kamel, D. Flandre and J.-D. Legat: “Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic”, in Proc. IEEE/ACM International Symposium Low-Power Electronics and Design, pp. 3-8, 2009. Acceptance rate: 24%. [pdf] Compact models are available here.
• C. Hocqet, D. Bol, D. Kamel and J.-D. Legat: “Assesment of 65nm subthreshold logic for smart RFID applications”, in Proc. Workshop Faible Tension Faible Consommation (FTFC), 4 p., 2009. [pdf]
  
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications”, in Proc. IEEE International SOI Conference, 2 p., 2008. This poster presentation was awarded as Best Poster of the conference. [pdf] Compact models are available here.
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Analysis and minimization of practical energy in 45nm subthreshold logic circuits”, in Proc. IEEE International Conference Computer Design, pp. 294-300, 2008. This paper was awarded as Best Paper of the conference. [pdf]
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Channel length upsize for robust and compact subthreshold SRAM”, in Proc. Workshop Faible Tension Faible Consommation (FTFC), pp. 117-120, 2008. [pdf]
• J. De Vos, D. Bol and D. Flandre: “Cellule SRAM 12 transistors à ultra faible courant de fuite”, in Proc. Workshop Faible Tension Faible Consommation (FTFC), pp. 111-115, 2008. [pdf]
• C. Roda Neve, D. Bol, R. Ambroise, D. Flandre and J.-P. Raskin: “Digital substrate noise reduction by low-power circuit operation and SOI technology”, in Proc. Workshop Faible Tension Faible Consommation (FTFC), pp. 23-28, 2008. [pdf]
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Impact of technology scaling on digital subthreshold circuits”, in Proc. IEEE Comp. Soc. Int. Conf. VLSI, pp. 179-184, 2008. [pdf]
• D. Bol, D. Flandre and J.-D. Legat: “Ultra-Low-Power Logic Style for Low-Frequency High-Temperature Applications”, in Proc. EuroSOI workshop, pp. 33-34, 2008. [pdf]
  
• D. Bol, R. Ambroise, D. Flandre and J.-D. Legat: “Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices”, in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, 4p., 2007. [pdf]
• D. Bol, R. Ambroise, C. Roda Neve, J.-P. Raskin and D. Flandre: “Wide-Band Characterization and Modeling of Digital Substrate Noise in SOI Technology”, in Proc. IEEE SOI Conference, pp. 133-134, 2007. [pdf] 

• D. Bol, “Pushing ultra-low-power digital circuits into the nanometer era”, Ph.D dissertation, Université catholique de Louvain, 219 p., 2008. [pdf] [slides]

• D. Bol, D. Flandre and J.-D. Legat, “Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic”, 6 p., available at www.soiconsortium.org, 2009. [pdf]

• D. Flandre, O. Bulteel, G. Gosset, B. Rue and D. Bol, “Ultra-low-power analog and digital circuits and Microsystems using disruptive ultra-low-leakage design techniques”, Int. Caribbean Conf. on Devices, Circuits and Syst., 2012.
  
• D. Bol, “Green SoCs for a Sustainable Internet-of-Things World”, at ST Microelectronics Crolles and CSEM Neuchâtel, 2012.
• D. Bol, “Electronics and the Environment – An Introduction”, at Université catholique de Louvain, 2011. [slides]
• D. Flandre, O. Bulteel, G. Gosset, B. Rue and D. Bol, “Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems”, FTFC workshop, 2011. [abstract]
• D. Bol, C. Hocquet, D. Kamel, J. De Vos, D. Flandre and J.-D. Legat, “Ultra-low-voltage design of nanometer CMOS circuits for smart energy-autonomous systems”, at the Berkeley Wireless Research Center weekly seminar, 2010. [abstract] [slides]
• D. Bol, “Ultra-low-voltage design of nanometer CMOS circuits for low-power heterogenuous embedded systems”, at  Ecole d'Hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH), 2010. [abstract] [slides]
• D. Bol, “Digital design on SOI in the nanometer era - from high-performance to ultra-low-power circuits”, in tutorial on “SOI design” of the 5th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EuroSOI), 2009. [slides]
• D. Bol and D. Flandre, “Fully-depleted SOI for nanometer subthreshold circuits”, in tutorial on “FD SOI” of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (EuroSOI), 2008.
• D. Bol and D. Flandre, “Technology scaling for ultra-low-power circuits – Is mainstream technology adapted to special design ?”, in tutorial on “Process and device issues from a circuit point of view” at the 9th Conference on Ultimate Integration on Silicon (ULIS) and in tutorial on “Ultra-low-power design” at the Workshop Faible Tension Faible Consommation (FTFC), 2008.

Patent

• D. Bol, D. Flandre and J.-D. Legat, “Ultra-low-power circuits”, European patent EP2008/055239, 2008.